1. Field of the Invention
The present invention relates to a method of manufacturing semiconductor devices, and in particular, to a method of manufacturing a semiconductor device comprising flash-memory type non-volatile semiconductor memory cells having a multi-layered floating gate electrode.
2. Description of the Prior Art
In recent years, much attention has been paid to flash memories that are non-volatile semiconductor devices capable of electrically deleting the entire cell array at the same time. In such a flash memory, a single memory cell is constructed by forming on a P-type silicon substrate, N-type source and drain regions at the respective ends of a gate structure, wherein the gate structure includes a first gate insulating film comprising a silicon oxide film, a floating gate electrode comprising a polycrystalline silicon film, a second gate insulating film comprising a silicon oxide film and a silicon nitride film, and a control gate electrode comprising a polycrystalline silicon film, the films and electrodes being laminated in the named order.
A non-volatile semiconductor memory induces and retains charges in the electrically insulated floating gate electrode as stored information. Information is written by injecting electrons into the floating gate electrode through the first gate insulating film which is a silicon oxide film. Information is deleted by applying a positive voltage to the source region as a deletion voltage and grounding the control gate electrode to produce a tunneling current passing the electrons through the silicon oxide first gate insulating film, thereby discharging the electrons to the source region.
As described above, since the flash memory electrically deletes a large number of non-volatile memory cells at the same time, the voltage required to delete, which hereinafter will be called the deletion voltage, must be constant throughout all the cells.
If, however, the polycrystalline silicon constituting the floating gate electrode in contact with the first gate insulating film has a large grain size, the required deletion voltage varies significantly among the cells because the degree of electric field localization varies depending on the crystallographic directions of the grains. Therefore, among the large number of total cells to be deleted, some cells may be deleted before it is desired. This means that there exists some faulty cells that exhibit an excess deletion type failure.
To eliminate this inconvenience, Japanese Unexamined Patent Application, JP-A-6-29540 discloses a floating gate electrode structure wherein the polycrystalline silicon constituting a floating gate electrode in contact with a first insulating tunnel oxide film has a small grain size. This prior art technique will next be described with reference to FIG. 8.
FIG. 8 is a cross sectional view showing the formation of floating gate electrodes for two adjacent memory cells. First, N-type source and N-type drain regions 44 are formed on a surface element region of a P-type silicon substrate 41. A field oxide film 42 that serves to divide the element region into island-like sections is formed on the N-type source and the N-type drain regions 44, and a silicon oxide film 43 is formed on the surface of the element region between the source region 44 and the drain region 44 as a first gate insulating film.
After forming the silicon oxide film 43, a polycrystalline silicon film 45 is formed on top of the silicon oxide film 43 to have a thickness of about 30 to 50 nm. The obtained structure is then annealed in N.sub.2 gas at a relatively low temperature of 700.degree. to 800.degree. C. or left at room temperature for a short period of time to form a silicon oxide film 46 of about 2 to 3 nm in thickness on the surface of the polycrystalline silicon film 45. Then, a thick polycrystalline silicon film 47 having a thickness required as a floating gate electrode is formed on the silicon oxide film 46.
The polycrystalline silicon film 47, silicon oxide film 46, and polycrystalline silicon film 45, all of which are laminated, are patterned to form a floating gate electrode 48. Phosphorous is ion-implanted as an N-type impurity into the polycrystalline silicon film 47 located at the top of the floating gate electrode structure. The structure is then annealed to introduce, through the thin silicon oxide film 46, the phosphorous into the thin polycrystalline silicon film 45 located at the bottom.
A second gate insulating film is subsequently formed on the floating gate electrode 48, and a control gate electrode comprising a polycrystalline silicon film is formed on the second gate insulating film.
In this prior art structure, that part of the floating gate electrode 48 which comes in contact with the tunnel silicon oxide film 43 is comprised of polycrystalline silicon film 45 that is very thin. Thus, the polycrystalline silicon film 45 has a small grain size. Therefore, the variation in the degree of electric field localization dug to the varying crystallographic directions of grains is negligible, and the required deletion voltage is expected to be uniform among different cells.
In the above prior art, however, when the silicon oxide film 46 is formed by annealing in N.sub.2 or left at room temperature, the semiconductor wafer is removed from a Chemical Vapor Deposition (CVD) furnace in which the polycrystalline silicon film 45 is formed, and is either transferred to an N.sub.2 annealing furnace in which the silicon oxide film 46 is formed or is left exposed to the air atmosphere of the room at room temperature. In either case, the top surface of the thin polycrystalline silicon film 45 is exposed to the atmosphere, i.e., air in the room, etc, containing contaminants such as boron, carbon, metal atoms, or organic substances. These contaminants present in the atmosphere stick to the surface of the thin polycrystalline silicon film 45.
The prior art non-volatile memory manufactured according to FIG. 8 thus has interfacial levels at the interface between the floating gate electrode and the tunnel oxide film or impurity related levels within the tunnel oxide film itself. This results in higher occurrence frequency of excess deletion failure in a non-volatile memory manufactured according to FIG. 8 as compared with a more conventional non-volatile memory with a floating gate electrode comprising only a single layer of polycrystalline silicon film. The occurrence frequencies of excess deletion of the prior art non-volatile memory of FIG. 8 and the conventional single layer floating gate electrode type non-volatile memories are shown as distributions 200 and 100, respectively, in FIG. 9. It can be seen that at times the prior art memories are inferior to the more primitive conventional memories.
The prior art technique may also cause a significant distribution in deletion voltage among memories fabricated using different fabrication apparatuses. These drawbacks tend to result in adverse effects. In addition, with this prior art technique, the yield is unstable, because the mounts of contaminants contained in the atmosphere are not constant even in the clean rooms where these semiconductor devices are manufactured.
Furthermore, if a floating gate electrode of a three-layer structure as is shown in FIG. 8 is to be constructed by forming a polycrystalline silicon film at the bottom using a CVD apparatus, then by forming outside the CVD apparatus, a silicon oxide film sandwiched by top and bottom layers, and then by forming a polycrystalline silicon film located at the top again using the CVD apparatus, the number of manufacturing steps must be increased and the throughput is thus degraded compared with the manufacture of a floating gate electrode comprising a single layer of polycrystalline silicon film. If a surface cleaning step is added to remove contaminants such as boron, carbon, metal atoms, and organic substances stuck to the structure during the formation of the silicon oxide film, the throughput may be further degraded.